United states patent application publication US 2005/0185446 describes a method for reducing non-uniformity or topography variation between an array and circuitry in a process for manufacturing semiconductor integrated non-volatile memory devices. This prior art document discloses a method in which an intermediate stack of multiple layers is provided during the manufacturing steps of gates structures in both the memory cell array and peripheral circuitry areas which contain logic circuitry. A thin stack comprising at least a thin dielectric layer and a third conductive layer is provided over a second conductive layer before the step of defining the control gate structures in the array and the single gates in the peripheral circuitry. This intermediate stack of multiple layers is used in order to compensate for thickness differences between the dual gate structures in the array and the single gate transistors in the peripheral circuitry.
However, a disadvantage of the method disclosed in this prior art document is that the intermediate stack requires a large amount of additional processing steps.